1. Field of the Invention
The present invention relates to an input buffer for a semiconductor device and, more particularly, to an input buffer for a semiconductor device receiving an external reference potential and an external signal obtained by superposing a logic signal of a small amplitude on the external reference potential, comparing the external reference potential with the external signal and applying an internal signal corresponding to the result of comparison to an internal circuitry.
2. Description of the Background Art
As the speed of operation of microprocessors has been increased recently, speed of operation of a memory has also been increased. As to data transfer between devices, however, the speed of operation is limited when the conventional TTL (Transistor Transistor Logic) based interface is used. TTL based interface does not present any problem as along as the operational frequency is low. However, when the operational frequency is made higher, an overshoot or an undershoot of an output signal is noticed and, in addition, in a bus transmission system, irregularity of signals caused by reflection has come to be a serious problem. In view of the foregoing, a high speed interface in which signal amplitude is made smaller, has come to be practically used.
FIG. 4 is a partially omitted circuit block diagram showing a structure of a semiconductor integrated circuit device (for example, DRAM) employing an LVTTL (Low Voltage Transistor Transistor Logic) interface, which is one of the TTL based interfaces.
Referring to FIG. 4, semiconductor integrated circuit device 30 includes input buffers 31.1 to 31.m, internal circuitry 32 and output buffers 33.1 to 33.n. Input buffers 31.1 to 31.m receive external signals EXT1 to EXTm and generate and apply to internal circuitry 32 internal signals. Internal circuitry 32 performs a prescribed operation (in case of a DRAM, data writing/reading operation) in accordance with the internal signals applied from input buffers 31.1 to 31.m. Output buffers 31.1 to 33.n amplify and externally output signals D1 to Dn generated by internal circuitry 32.
FIG. 5 is a circuit diagram showing a structure of input buffer 31.m shown in FIG. 4. Referring to FIG. 5, input buffer 31.m includes P channel MOS transistors 44, 45 and N channel MOS transistors 46, 47. P channel MOS transistors 44 and 45 are connected between a line of power supply potential Vdd (3.3V) and an output node N46, respectively. N channel MOS transistors 46 and 47 are connected in series between an output node N46 and a line of ground potential Vss. MOS transistors 44 and 47 receive at their gates an input signal VI (external signal EXTm), and MOS transistors 45 and 46 receive at their gates an activating signal EN. Activating signal EN is set to an inactive level of "L" in a standby mode (power down mode, sleep mode) of semiconductor integrated circuit device 30 so as to reduce power consumption. Potential of output node N46 will be the output signal VO.
When activating signal EN is at the inactive level of "L", P channel MOS transistor 45 is rendered conductive, N channel MOS transistor 46 is rendered non-conductive, and the output signal VO is fixed at the "H" level regardless of the input signal VI. When activating signal EN rises to the active level of "H", P channel MOS transistor 45 is rendered non-conductive, N channel MOS transistor 46 is rendered conductive and input buffer 31.m is activated.
When input signal VI rises to "H" level (2V), P channel transistor 44 is rendered non-conductive, N channel MOS transistor 47 is rendered conductive, and output signal VO falls to the "L" level. When the input signal VI falls to the "L" level (0.8V), P channel MOS transistor 44 is rendered conductive, N channel MOS transistor 47 is rendered non-conductive, and output signal VO rises to the "H" level.
FIG. 6 is a partially omitted circuit block diagram showing an SSTL.sub.-- 3 (Stub Series Terminated Logic for 3.3V) interface, which is a high speed interface.
Referring to FIG. 6, in SSTL.sub.-- 3 interface, an output node 51a of an output buffer 51 in a transmitting side semiconductor integrated circuit device 50 is connected by a signal transmission line 54 to one input node 53a of an input buffer 53 in a receiving side semiconductor integrated circuit device 52. Output node 51a of output buffer 51 and one input node 53a of input buffer 53 receive terminating potential Vtt (1.5V) through resistance elements 55 and 56, respectively. The other input node 53b of input buffer 53 receives a reference potential VR (1.5V).
As shown in FIG. 7, input buffer 53 is constituted by a differential amplifying circuit, and it includes P channel MOS transistors 60 to 62 and N channel MOS transistors 63 and 64. P channel MOS transistor 60 is connected between a line of power supply potential Vdd and a node N60, and receives at its gate an activating signal ZEN. MOS transistors 61 and 63 as well as MOS transistors 62 and 64 are connected in series between node N60 and a line of ground potential Vss, respectively. P channel MOS transistors 61 and 62 have their gates connected together to a drain (node N61) of P channel MOS transistor 61.
P channel MOS transistors 61 and 62 constitute a current mirror circuit. Gates of N channel MOS transistors 63 and 64 receive reference potential VR and input signal VI respectively. N channel MOS transistors 63 and 64 constitute a differential transistor pair. Input signal VI is a signal obtained by superposing a logic signal of small amplitude on reference potential VR, and it swings between 1.5+04V and 1.5-0.4V. A potential at node N62 between P channel MOS transistor 62 and N channel MOS transistor 64 will be the output signal VO.
When the activating signal ZEN is at the inactive level of "H", P channel MOS transistor 62 is rendered non-conductive, and the output signal VO is fixed at the "L" level regardless of the input signal VI. When the activating signal ZEN falls to the active level of "L", P channel MOS transistor 60 is rendered conductive, current is supplied to each of nodes N61 and N62, and input buffer 53 is activated.
When input signal VI rises to the "H" level (1.9V), resistance value of N channel MOS transistor 64 attains smaller than the resistance value of N channel MOS transistor 63, so that output signal VO falls to the "L" level. When the input signal VI falls to the "L" level (1.1V), resistance value of N channel MOS transistor 64 attains higher than the resistance value of N channel MOS transistor 63, so that the output signal VO rises to the "H" level.
In the SSTL.sub.-- 3 interface, the potential of signal transmission line 54 has a small amplitude, and therefore high speed signal transmission is possible. Further, AC component of consumed power can be reduced. Further, as power consumption of output buffer 51 is small, output buffer 51 can readily be integrated.
However, in the SSTL.sub.-- 3 interface, it is necessary that the signal transmission line 54 is held at the terminating potential Vtt. Therefore, power is consumed to generate the terminating potential Vtt from power supply potential Vdd, which leads to the problem that power consumption of the overall system is increased. This is especially problematic in a system driven by a battery, such as a portable equipment.
Accordingly, a method has been proposed in which the terminating potential Vtt is set to be the same as power supply potential Vdd (3.3V), reference potential VR is set to 2.9V and the input signal VI is adapted to swing between 2.9+0.4V and 2.9-0.4V, as shown in FIG. 9. According to this method, the power consumed for generating terminating potential Vtt is eliminated, and therefore power consumption of the overall system can be reduced. However, in this method, the terminating potential Vtt is not the same as reference potential VR, and therefore the transition of the signal VI from "H" to "L" level is not balanced with transition from "L" to "H" level, and therefore the method is not suitable for high speed operation.
Therefore, another method has been proposed in which terminating potential Vtt is set to the power supply potential Vtt when the system is battery driven so that reduction in power consumption is given higher priority than high speed operation, while the terminating potential Vtt is set to an intermediate potential of 0.45.times.Vdd when the system is not battery driven but driven by the main power, so that high speed operation is given higher priority than reduction in power consumption.
In the input buffer 53 of FIG. 7, however, when terminating potential Vtt is set to the power supply potential Vdd and the reference potential VR is set to 2.9V, resistance value of N channel MOS transistor is made smaller as compared with the prior art example in which the terminating potential Vtt is set to the intermediate potential of 0.45.times.Vdd and reference potential VR to 1.5V, whereby intermediate level of logic amplitude of the output signal VO lowers as shown in FIG. 10, causing malfunction in the internal circuitry.
Further, according to the current trend of lowering power supply voltage of the semiconductor devices from 3.3V to 2.5V, lowering of input/output voltages has been required. In a 3.3V system, SSTL.sub.-- 3 interface has been standardized, while an SSTL.sub.-- 2 interface has been standardized for a 2.5V system. There is a demand to the side of the semiconductor device that semiconductor devices having the same structure should cope with both SSTL.sub.-- 2 and SSTL.sub.-- 3 interfaces.
In the SSTL.sub.-- 2 interface, however, reference potential VR is 1.25V. Therefore, resistance value of N channel MOS transistor attains higher than when the reference potential VR is 1.5V, and therefore an intermediate level of the logic amplitude of output signal VO increases as shown in FIG. 10, resulting in malfunction of the internal circuitry.